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Journal Conference Publications

Journal / Conference Publications

 Publications in 2013-14

  1. Sneh lata Murotiya and Anu gupta (2013), " Design of CNTFET based 2-bit ternary ALU for nano-electronics, International Journal of Electronics, Taylor & Francis, DOI: 10.1080/00207217.2013.828. and Parallel Systems (IJCSI), Volume 1, No 2, September 2013.
  2. Sneh lata Murotiya and Anu gupta (2014), " Design of content-addressable memory cell using CNTFETs", International Journal of Electronics Letters ,Taylor & Francis DOI: 10.1080/21681724.2014.911368
  3. Priya Gupta, Anu Gupta and Abhijit Asati “A Review on Ultra Low Power Design Technique: Sub-threshold Logic ” International Journal of Computer Science and Technology-IJCST,Vol.4, Issue Spl-2, April-June 2013, ISSN: 0976-8491 (Online) ISSN : 2229-4333 (Print)
  4. Sneh Lata Murotiya and Anu gupta (2013), “Design of CNTFET-based Radiation hardened Latches” European Journal of Scientific Research, Volume 117 Issue 1
  5. Anu Gupta, Raj Singh Dua, " A Novel Ultra Low Power, High Impedance Current Mirror Circuit for Biasing Operational Amplifier in Sub-threshold Region", International Journal of New Innovations in Engineering and Technology (IJNIET), Vol. 1 Issue 3 February 2013, ISSN: 2319-6319, pp-93
  6. Sachin Maheshwari, Rameez Raza, Pramod Kumar and Dr. Anu Gupta, " Convex Optimization of Energy and Delay using Logical Effort Method in Deep Sub-Micron Technology" Proc. of the 17th International Symposium on VLSI Design and Test (VDAT 2013), July 27-30, Malaviya National Institute of Technology (MNIT), Jaipur, India, 2013.
  7. Sachin Maheshwari, Himadri Singh Raghav and Anu Gupta, " Characterization of Logical Effort for Improved Delay" Proc. of the 17th International Symposium on VLSI Design and Test (VDAT 2013), July 27-30, Malaviya National Institute of Technology (MNIT) Jaipur, India, 2013.
  8. Priya Gupta, Anu Gupta and Abhijit Asati “A Review on Ultra Low Power Design Technique: Sub-threshold Logic ” International Journal of Computer Science and Technology-IJCST,Vol.4, Issue Spl-2, April-June 2013, ISSN: 0976-8491 (Online) ISSN : 2229-4333 (Print)
  9. Sachin Maheshwari, Himadri Singh Raghav and Anu Gupta, " Characterization of Logical Effort for Improved Delay" VLSI Design and Test, Communications in Computer and Information Science, Vol. 382, pp. 108–117, 2013. (© Springer-Verlag Berlin Heidelberg 2013).
  10. Sachin Maheshwari, Rameez Raza, Pramod Kumar and Dr. Anu Gupta, "Convex Optimization of Energy and Delay using Logical Effort Method in Deep Sub-Micron Technology" VLSI Design and Test, Communications in Computer and Information Science, Vol. 382, pp. 185–193, 2013. (© Springer-Verlag Berlin Heidelberg 2013
  11. Sneh Lata Murotiya, Anu Gupta, "CNTFET Based Design of Content Addressable Memory Cells", 4th IEEE ICCCT – 2013, MNNIT Allahabad, pp.1-4, Sep.20-22, 2013.
  12. Sneh Lata Murotiya, Anu Gupta, “Performance Evaluation of CNTFET based Dynamic Dual Edge Triggered Register”, 1st IEEE ICAES – 2013, CEERI Pilani, pp. 180-183, Sep. 21-23, 2013.
  13. Sneh Lata Murotiya, Anu Gupta, “DESIGN AND ANALYSIS OF CNTFET BASED D FLIP-FLOP”, presented in ICCS – 2013, BKBIET Pilani and published in IJECET, vol.4, issue 7 pp. 144-149, 2013
  14. Sneh Lata Murotiya, Anu Gupta, “Performance Evaluation of CNTFET based DTCAM cell”, IEEE Conference INDICON – 2013, IIT Mumbai.
  15. Priya Gupta, Akshay Kumar Sharma, Pratishtha Dehadray, Anu Gupta “Design and Implementation of low power TG Full Adder design in subthreshold regime” IEEE International Conference on Intelligent Interactive Systems and Assistive Technologies, August 2-3, 2013, Coimbatore, INDIA
  16.  Priya Gupta, Ishan Munje, Nikhil Kaswan , Anu Gupta , Abhijit Asati  “Analysis & Implementation of Ultra Low-Power 4-bit CLA in subthreshold regime” Selected to be published on IEEE International Conference on Circuit, Power and Computing Technologies” (ICCPCT), March 20th-21st 2014, Tamilnadu . Research Institute, Pilani, September 21-23, 2013
  17. Nikhil Kaswan , Ishan Munje, Yash Kothari , Priya Gupta, Anu Gupta “Implementation of high speed energy efficient 4-bit binary CLA based incrementer /decrementer”  in 2013 International Conference on Advanced Electronic Systems (ICAES),  Sept. 21-23 2013, CEERI Pilani.
  18. Abhilash K N, Shakthi Bose, Anu Gupta, " Abhilash K N, Shakthi Bose, Anu Gupta, " A High Gain, High CMRR Two-Stage Fully Differential Amplifier Using gm/Id technique for Bio-medical Applications", IEEE PrimeAsia 2013 Conference held at GITAM University, Visakhapatnam Campus, 19th -21st December 2013
  19. Siddharth Malhotra , Abhinav Mishra, Rakesh B R , Anu Gupta, "Frequency Compensation in Two-Stage Operational Amplifiers for Achieving High 3-dB Bandwidth” IEEE PrimeAsia 2013 Conference held at GITAM University, Visakhapatnam Campus, 19th -21st December 2013
  20. Ganesh Raj, Ankur Gupta , Dr. Anu Gupta, " Self timed High speed 8-bit SAR ADC in 0.35um", IEEE Conference INDICON – 2013, IIT Mumbai
  21. Jaskaran Singh Grover , Anu Gupta ,"Studying Crosstalk Trends for Signal Integrity on Interconnects using Finite Element Modeling", COMSOL Conference 2013 October 17 - 18, 2013, Bangalore
  22. Sivaram Prasad Kopparthy, Ishit Makwana, Anu Gupta, “An Asynchronous 8-bit 5 MS/s Pipelined ADC for Biomedical Sensor based Applications”, International Conference on Electronics, Computing and Communication Technologies (IEEE CONECCT) , Jan 17-19, 2013World Trade Center, Bangalore, India
Complete Publications list (Title of paper, authors, Journal details, pages, year etc.):

 International Journals

 1.      Anu Gupta, Chandra Shekhar, “Performance exploration of adder architectures for small to moderate-sized low power, high performance adders” , Journal of Microelectronics International, Vol. 22 No. 3, 2005, pp-20-27

2.      Anu Gupta, Bipin Naraynan Kulkarni, “Automation of Clock Distribution Network Design for Digital Integrated Circuits using Divide and Conquer technique” , Integration, the VLSI Journal, Vol. 39, issue 4, pp 407-419, ELSEVIER, 2006, pp-407-419

3.      Nikhil Bhattar, Anu Gupta, “On-chip resistors can make a stable current reference”, Potentials, IEEE, Volume: 27,  Issue: 1, 2008, pp-31-36

4.      Maneesh Menon, Robin Paul Prakash, Anu Gupta, “Design of 10-bit Digital to Analog Converter Using Cascaded Operational Amplifier Topology”, International Journal of Recent Trends in Engineering, Vol.1, No. 4, May 2009

5.      S K Sahoo, Anu Gupta,  Abhijit Asati, Chandra Shekhar, “A Novel Redundant Binary Number to Natural Binary Number Converter,” Journal of VLSI Signal Processing Systems, 2009

6.      S K Sahoo, Chandra Shekhar, Sudeepti   Kodali, Abhijit R. Asati and  Anu Gupta, “Dual Channel Addition Based FFT Processor Architecture for Signal and Image Processing” , Int. J. High Performance Systems Architecture, Vol. 2, No. 1, 2009, pp-35-45.

7.      Anirban Chatterjee, Sankha Subhra Saha, Rishabh Gupta, Anu Gupta , “A Comparative Exploration of Sample and Hold architectures using Verilog AMS International Journal of Engineering and Innovative Technology (IJEIT) Volume 1, Issue 5, May 2012, pp-260-264

8.      Sachin Maheshwari, Amitoj Singh and Anu Gupta, “Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology”, “International Journal of Advances in Electronics Engineering, Vol.2 Issue 2, 2012.

9.      Ashray Vinayak Gogte, Anu Gupta, “Low Power Temperature Compensated CMOS
Current Reference”, International Journal of Recent Trends in Engineering ,Vol 1, No. 3, May 2009 , pp-287-289

10. Sneh Lata Murotiya, Aravind Matta & Anu Gupta, "Performance Evalution Of CNTFET-Based Sram Cell Design", International Journal of Electrical and Electronics Engineering (IJEEE) ISSN (PRINT): 2231 – 5284, Vol-2, Iss-1, 2012

11. Anu Gupta, Raj Singh Dua, " A Novel Ultra Low Power, High Impedance Current Mirror Circuit for Biasing Operational Amplifier in Sub-threshold Region", International Journal of New Innovations in Engineering and Technology (IJNIET), Vol. 1 Issue 3 February 2013, ISSN: 2319-6319, pp-93

12. Priya Gupta, Anu Gupta and Abhijit Asati “A Review on Ultra Low Power Design Technique: Sub-threshold Logic ” International Journal of Computer Science and Technology-IJCST,Vol.4, Issue Spl-2, April-June 2013, ISSN: 0976-8491 (Online) ISSN : 2229-4333 (Print)

13.  Sneh Lata Murotiya and Anu Gupta (2013), “Design of CNTFET-based Radiation hardened Latches” European Journal of Scientific Research, Volume 117 Issue 1.

14. Sneh lata Murotiya and Anu Gupta (2013), " Design of CNTFET based 2-bit ternary ALU for nano-electronics, International Journal of Electronics, Taylor & Francis, DOI: 10.1080/00207217.2013.828. and Parallel Systems (IJCSI), Volume 1, No 2, September 2013.

15. Sneh lata Murotiya and Anu Gupta (2014), " Design of content-addressable memory cell using CNTFETs", International Journal of Electronics Letters ,Taylor & Francis DOI: 10.1080/21681724.2014.911368

 Indian  Journals

  1. Anu Gupta, & Ganesh TS, “A Comparison of Adiabatic Logic Circuit Techniques for an Energy Efficient 1-bit Full Adder Design”, Journal of Research, IETE, Volume 50, No. 1, Jan.-Feb. 2004, pp-29 – 36

National Conferences


  1. Anu Gupta, & Chandrashekhar, “Adder Architectures for fully static and complementary pass logic designs” , Proceedings of the national seminar on VLSI: Systems, Design and Technology, IIT Bombay, Dec. 10-11, 2000, pp-140-145
  2. Anu Gupta, & Chandrashekhar, “Design Exploration of Architecture for Optimal Adder Synthesis”, IETE Golden Jubilee Seminar on Electronic Design Automation: Issues and Challenges, April 26, 2003, pp-4-
  3.   S K Sahoo, Chandra Shekhar, Anu Gupta, “A Compact Fast Parallel Multiplier Using Modified Equivalent Binary Conversion Algorithm”, Proceedings of VLSI Design and Test Workshop , Aug. 26-28, 2004
  4.  Arpit Kumar Gupta, Anu Gupta, A Design Methodology for Efficient Design of fully differential OP AMP as a Voltage Buffer.”, IMS Conference-2006, Electronics Science Department, Kurukshetra university, Kurukshetra, February 17-18, 2006.
  5. Anu Gupta, Ninad B Kothari, “Effect of Transistor Sizing in Design of an Energy Efficient 1-bit Full Adder Design using different Adiabatic Logic Circuit Techniques”, IMS Conference-2006, Electronics Science Department, Kurukshetra university, Kurukshetra, February 17-18, 2006
  6. Tushar Uttarwar, Sanket Jain,  Anu Gupta,       Nitin Chaturvedi, “A High Performance, Low Power, Fully Differential Telescopic Amplifier”, Advances in Electronic System Design (AESD'08) conference, ATMIYA CONFERENCE CLUSTER 2008 (ACC '2008), November 20 - 23, 2008 at AITS, Rajkot (GUJARAT)
  7. Ashray Vinayak Gogte, Anu Gupta, “A new temperature compensated CMOS current reference”, International conference on multimedia signal processing and communication technologies , 14 -16 March 2009 Zakir Husain college of Engineering & Technology , Aligarh muslim university
  8. Gaurav Agarwal, Amit Singhal, Anu Gupta, Prayush Kumar, “Hardware Implementation of Delighting Module for Using it in a Digital Camera Chip”, Proceeding Of 13th IEEE VLSI Design And Test Symposium held on  July 8-10, 2009, Bangalore, pp-96-104
  9. Raj Dua, Sumeet Tiwana, Anu Gupta, “Ultra Low Power Digital to Analog Converter “,Progress In Vlsi Design And Test 2009, Proceeding Of 13th IEEE VLSI Design And Test Symposium held on  July 8-10, 2009, Bangalore, pp-271-27
  10. Raj Singh Dua, Anu Gupta, “A Novel Ultra Low Power Current Mirror Circuit for Biasing Operational Amplifier in Sub-threshold Region for Virtual Instrumentation Systems”, National Conference On Virtual And Intelligent Instrumentation( Ncvii-09), 13-14 Nov. 2009, BITS, Pilani , Rajasthan
  11. Hariprasad Chandrakumar , Anu Gupta, “A Micropower Low-noise CMOS Neural Amplifier for Bio-medical Instrumentation”, National Conference On Virtual And Intelligent Instrumentation( Ncvii-09), 13-14 Nov. 2009, BITS, Pilani , Rajasthan
  12. Sneh Lata Murotiya and Anu Gupta, “An Exploration of VLSI parallel Adder using Carbon NanoTube Field Effect Transistor,” Souvenir of National Conference on VLSI Design and Embedded Systems, CEERI, Pilani, pp-7A.5, October 12-14, 2011
  13. Anu Gupta and Subhrojyoti Sarkar, “An Efficient High Frequency and Low Power Analog Multiplier in Current Domain,” Proceedings of 16th International Symposium, pp-1-9, VDAT 2012, Shibpur, India, July 1-4, 2012
  14. Sivaram Prasad Kopparthy, Ishit Makwana, Anu Gupta, “Asynchronous 8-bit Pipelined ADC for Self-Triggered Sensor based Applications”, Asia-Pacific Conference on Postgraduate Research in Microelectronics & Electronics (Prime Asia), Dec 5-7 2012, BITS-Pilani, Hyderabad Campus
  15. Sneh Lata Murotiya, Aravind Matta and Anu Gupta, “Performance evaluation of CNTFET based SRAM cell design.” Proc. of Inter National Conference on Electrical Engineering and Computer Science,”, May 12, 2012, Trivandrum, Kerala, pp-88-92
  16. Sivaram Prasad Kopparthy, Ishit Makwana, Anu Gupta, “An Asynchronous 8-bit 5 MS/s Pipelined ADC for Biomedical Sensor based Applications”, International Conference on Electronics, Computing and Communication Technologies (IEEE CONECCT) , Jan 17-19, 2013World Trade Center, Bangalore, India
  17. Amit Agarkhed, Sharvil Patil, Anu Gupta, “Improved Implementation of CRL and SCRL Gates for Ultra-Low Power”, International conference on advances in recent technologies in communication and comutind, ARTCOM 2009, Technically Co-sponsored by the IEEE-Computational Intelligence Society, Kottayam, Kerala India., 27 - 28 Oct 2009
  18. Ashutosh Mehra, Anu Gupta, Sharvil Patil, Abhishek Mehra, “A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers”, International conference on advances in recent technologies in communication and computing, ARTCOM 2009, Technically Co-sponsored by the IEEE-Computational Intelligence Society, Kottayam, Kerala India., 27 - 28 Oct 2009
  19. Vivek Gupta, Anu Gupta, Nitin Chaturvedi, Abhijit Asati, “A Novel Technique for Improvement of Power Supply Rejection Ratio in Amplifer Circuits “, International Conference on Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT '09.  December 28-29, 2009, Trivandrum, Kerala, India (paper is archived in the IEEE Xplore), pp-756 – 758
  20. Maneesh Menon, Karan Dhall, Anu Gupta, Nitin Chaturvedi , “High bandwidth Low Power Cascaded Three Stage Amplifier with Multi-path Nested Miller Compensation for high performance IC Applications”, International Conference on Recent Trends in Information, Telecommunication and Computing – ITC 2010, March 12-13, 2010 in Kochi, Kerala, India, Paper is archived in the IEEE Xplore, pp-9 – 12
  21. Anu Gupta, Jithin P. Thomas, K.R.S.N. Kumar, Vamsidhar Addanki, Nitin Chaturvedi, “Hardware Implementation of a biometric fingerprint Identification System”, International Joint Journal Conference in Computer, Electronics and Electrical, CEE 2010
  22. Gaurav Jain,Vaibhav Gogte, Shivani Bathla, Anu Gupta, “An Exploration of Efficient Architecture for Double Data Rate SDRAM for a High Performance Implementation, International Conference on Advances in Electrical & Electronics (AEE), Dec 20-21 2011 in Noida, India
  23. Himadri Raghav, Sachin Maheshwari, Anu Gupta, “A Comparative Analysis of Power & Delay Optimize Digital Logic Families for High Performance System Design", International Conference on Electronic Systems (ICES 2011), NIT Rourkela
  24. Anu Gupta, Mohammad Waqar Ahamed, Abhishek Dhir , Ravish Soni, Neeraj Kumar Sharma, “ Novel Method To Implement High Frequency All Digital Phase-Locked Loop On FPGA”, International Conference on VLSI & Communication Systems , SAINTGITS College of Engineering, Pathamuttom, Kotyam, Keral
  25. Gaurav Jain, Vaibhav Gogte, Shivani Bathla,  Anu Gupta, “An Exploration of Efficient Architecture for Double Data Rate SDRAM for a High Performance Implementation, “International Conference on Advances in Electrical & Electronics (AEE), Noida, India , Dec 20-21 2011, Paper ID-AET_AEE_507
  26. Sachin Maheshwari, Amitoj Singh and Dr. Anu Gupta, "Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology", Proc. of the Int. Conf. on Advances in Computer, Electronics and Electrical Engineering (ICACEEE-2012), March 25-27, Mumbai, pp. 91-95, 2012. (ISBN: 978-981-07-1847-3). (Also published in UACEE International Journal of Advances in Electronics Engineering, Vol. 2, Issue 2, pp. 39-43, ISSN 2278 - 215X [Online]
  27. Sneh Lata Murotiya, Aravind Matta, Anu Gupta, “Performance evaluation of CNTFET based SRAM cell design.” Proc.of International Conference on Electrical Engineering and Computer Science,” pp-88-92, May 12, 2012, Trivandrum, Kerala
  28. Sachin Maheshwari, Rameez Raza, Pramod Kumar and  Anu Gupta, " Convex Optimization of Energy and Delay using Logical Effort Method in Deep Sub-Micron Technology" Proc. of the 17th International Symposium on VLSI Design and Test (VDAT 2013), July 27-30, Malaviya National Institute of Technology (MNIT), Jaipur, India, 2013. 
  29. Sachin Maheshwari, Himadri Singh Raghav and  Anu Gupta, " Characterization of Logical Effort for Improved Delay" Proc. of the 17th International Symposium on VLSI Design and Test (VDAT 2013), July 27-30, Malaviya National Institute of Technology (MNIT) Jaipur, India, 2013. 
  30. Priya Gupta, Anu Gupta and Abhijit Asati “A Review on Ultra Low Power Design Technique: Sub-threshold Logic ” International Journal of Computer Science and Technology-IJCST,Vol.4, Issue Spl-2, April-June 2013, ISSN: 0976-8491 (Online) ISSN : 2229-4333 (Print)
  31. Sachin Maheshwari, Himadri Singh Raghav and Dr. Anu Gupta, " Characterization of Logical Effort for Improved Delay" VLSI Design and Test, Communications in Computer and Information Science, Vol. 382, pp. 108–117, 2013. (© Springer-Verlag Berlin Heidelberg 2013).
  32. Sachin Maheshwari, Rameez Raza, Pramod Kumar and Dr. Anu Gupta, "Convex Optimization of Energy and Delay using Logical Effort Method in Deep Sub-Micron Technology" VLSI Design and Test, Communications in Computer and Information Science, Vol. 382, pp. 185–193, 2013. (© Springer-Verlag Berlin Heidelberg 2013
  33. Sneh Lata Murotiya, Anu Gupta, "CNTFET Based Design of Content Addressable Memory Cells", 4th IEEE ICCCT – 2013, MNNIT Allahabad, pp.1-4, Sep.20-22, 2013.
  34. Sneh Lata Murotiya, Anu Gupta, “Performance Evaluation of CNTFET based Dynamic Dual Edge Triggered Register”, 1st IEEE ICAES – 2013, CEERI Pilani, pp. 180-183, Sep. 21-23, 2013.
  35. Sneh Lata Murotiya, Anu Gupta, “DESIGN AND ANALYSIS OF CNTFET BASED D FLIP-FLOP”, presented in ICCS – 2013, BKBIET Pilani and published in IJECET, vol.4, issue 7 pp. 144-149, 2013.
  36. Sneh Lata Murotiya, Anu Gupta, “Performance Evaluation of CNTFET based DTCAM cell”, IEEE Conference INDICON – 2013, IIT Mumbai.
  37. Priya Gupta, Akshay Kumar Sharma, Pratishtha Dehadray, Anu Gupta “Design and Implementation of low power TG Full Adder design in subthreshold regime” IEEE International Conference on Intelligent Interactive Systems and Assistive Technologies, August 2-3, 2013, Coimbatore, INDIA
  38. Priya Gupta, Ishan Munje, Nikhil Kaswan , Anu Gupta , Abhijit Asati  “Analysis & Implementation of Ultra Low-Power 4-bit CLA in subthreshold regime” Selected to be published on IEEE International Conference on Circuit, Power and Computing Technologies” (ICCPCT), March 20th-21st 2014, Tamilnadu . Research Institute, Pilani, September 21-23, 2013
  39. Nikhil Kaswan , Ishan Munje, Yash Kothari , Priya Gupta, Anu Gupta “Implementation of high speed energy efficient 4-bit binary CLA based incrementer /decrementer”  in 2013 International Conference on Advanced Electronic Systems (ICAES),  Sept. 21-23 2013, CEERI Pilani.
  40. Abhilash K N, Shakthi Bose, Anu Gupta, " Abhilash K N, Shakthi Bose, Anu Gupta, " A High Gain, High CMRR Two-Stage Fully Differential Amplifier Using gm/Id technique for Bio-medical Applications", IEEE PrimeAsia 2013 Conference held at GITAM University, Visakhapatnam Campus, 19th -21st December 2013
  41. Siddharth Malhotra , Abhinav Mishra, Rakesh B R , Anu Gupta, "Frequency Compensation in Two-Stage Operational Amplifiers for Achieving High 3-dB Bandwidth” IEEE PrimeAsia 2013 Conference held at GITAM University, Visakhapatnam Campus, 19th -21st December 2013
  42. Ganesh Raj, Ankur Gupta , Dr. Anu Gupta, " Self timed High speed 8-bit SAR ADC in 0.35um", IEEE Conference INDICON – 2013, IIT Mumbai
  43. Jaskaran Singh Grover , Anu Gupta ,"Studying Crosstalk Trends for Signal Integrity on Interconnects using Finite Element Modeling", COMSOL Conference 2013 October 17 - 18, 2013, Bangalore

 International Conferences (abroad)

  1. Tushar Uttarwar, Sanket Jain,  Anu Gupta, “Design of a High Performance, Low Power, Fully Differential Telescopic Amplifier using Stable Common-Mode Feedback Circuit”, International Joint Conferences on Computer, Information and Systems Sciences and Engineering, December 5th  – 13th, 2008, Sponsored by University of Bridgeport, Technically co-sponsored by IEEE Computer Society and Communications Society
  2. Sameer Somvanshi , S C Bose, Anu Gupta,   “A novel sub-1 Volt Bandgap Reference with all CMOS”, Proceedings of the 12th WSEAS international conference on Circuits, Heraklion, Greece Year of Publication, 2008 , pp-232-237
  3. Cherin Joseph, Anu Gupta, “A novel hardware efficient Digital Neural Network architecture implemented in 130nm technology”, The 2nd International Conference on Computer and Automation Engineering (ICCAE), 2010, Paper is archived in the IEEE Xplore, pp-82-87

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