BITS Pilani

  • Page last updated on Friday, November 24, 2017

Digital Signal Processing Lab

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Digital Signal Processing Lab

Courses to cater

  • EEE F434 Digital Signal Processing
  • CS G553 Reconfigurable computing
  • EEE348  FPGA based systems design lab
  • EEE G512 Embedded systems design
  • EEE G626 Hardware Software  co-design

Facilities

Software
Vivado System Design Suite software for end to end design of system on chip (SoC) Design and implementing FPGA based applications. This suite includes the following tools:
Vivado RTL Design
  • Design entry using HDL software and/or IP catalog
  • Design for specific Xilinx boards and devices
  • Perform RTL analysis on the source file
  • Behavioral simulation of  the Design using the Vivado Simulator
  • I/O planning for a specific hardware.
  • Synthesize the Design
  • mplement the Design
  • Timing simulation of the implemented device.
  • Generate Bitstream, Configure Design and program  on FPGA
Vivado HLS
  • Design Entry using higher level languages like C, C++ and SystemC
  • C Simulation
  • C/RTL Co simulation
  • Export the high-level code to RTL
  • Create new IPs for use in Vivado
Vivado System Generator
  • System Generator for DSP™ is the industry’s leading high-level tool for designing high-performance DSP systems using Xilinx All Programmable devices.
  • Integrates RTL, embedded, IP, MATLAB and hardware components of a DSP system
  • DSP modeling using MATLAB Simulink
  • Automatic code generation of VHDL or Verilog from Simulink
  • Hardware co-simulation
Hardware ZedBoard:   Zynq™Evaluation and Development Hardware (19 Boards)
  • Evaluation and development board based on the Xilinx ZynqTM-7000 All Programmable SoC (AP SoC).
  • Combines a dual Corex-A9 Processing System (PS) with 85,000 Series-7 Programmable Logic (PL) cells.
  • Zynq-7000 AP SoC can be targeted for broad use in many applications.

Target Applications

  • Video processing
  • Motor control
  • Software acceleration
  • Linux/Android/RTOS development
  • Embedded ARM® processing
  • General Zynq®-7000 All Programmable SoC prototyping

People

  • Faculty: S K Sahoo, KCS Murti, Soumya J, Chetan Kumar
  • Lab Technician Bhasker, Srikanth

People

  • Faculty: S K Sahoo, KCS Murti, Soumya J, Chetan Kumar
  • Lab Technician Bhasker, Srikanth

News

 
[Project] Dr. Souvik Kundu (PI) and Prof. Souri Banerjee (Physics, co-PI) received a project from BRNS (3 years, ~35 lakhs) - "Metal-oxide and Nanocomposite based low-power non-volatile switching device".
 
[PhD Student Paper] Manu Gupta, V Rajagopalan, E P Pioro, B.V.V.S.N. Prabhakar Rao, Volumetric Analysis of MR Images for Glioma Classification and their Effect on Brain Tissues, Signal, Image and Video Processing, Published Online, 2017. 
 

Events

[15 Sep 2017Visit by Prof. R. Karmalkar, IIT Madras
 
[24 Aug 2017Visit by Prof. Varun Jeoti (Signal processing and Wireless communication), University Technology Petronas, Malaysia 
 
[11 Aug 2017Interaction with New EEE Students
 

Recent Publications

Detailed List...

1. Manu Gupta, V Rajagopalan, E P Pioro, B.V.V.S.N. Prabhakar Rao, Volumetric Analysis of MR Images for Glioma Classification and their Effect on Brain Tissues, Signal, Image and Video Processing, Published Online, 2017.  

2. S. Chitraganti, R. Toth, N. Meskin, J. Mohammadpour, Stochastic model predictive tracking of piecewise constant references for LPV  SystemsIET Control Theory & Applications, in press, 2017.

3. Soham Jariwala, Rohit Nagpal, Saksham Phul, Sanket Goel and Balaji Krishnamurthy, Modeling the performance of an enzymatic glucose fuel cell, accepted for publication with Journal of Electroanalytical Chemistry, 2017.

4. Venkateswaran PS, Santosh Dubey, Abhishek Sharma, Ajay Agarwal and Sanket Goel*, Stereolithographic 3D Printed Microfluidic viscometer for Rapid Detection of Automobile Fuel Adulteration, accepted for publication with Sensor Letters, 2017.

5. S. K. Sahoo, A. Gangishetty, R. Sahoo and M. Muglikar, High Performance Ternary Adder using CNTFET, IEEE Transactions on Nanotechnology , Vol. 99, pp.1-1. 2017.

6. Young Ho Kim, Jeong-Woo Sohn,  Yeon Kyung Lee, Jaehoon Jung, Minyeong Jeong, Sanket Goel, Hee Jin Kim,  Sang-June Choi, Preparation of pH Sensitive MMT/PEGMEA Nanocomposite Micropatterns by Rapid and Simple UV Curing Procedures,Journal of Nanoelectronics and Optoelectronics, Vol 12(6), pp. 550-556, 2017.

7. Ganesh Kumar Ganjikunta and Subhendu Kumar Sahoo, An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications, Integration, the VLSI Journal, Vol. 57, pp. 125-131, 2017.

8. Kotha Srinivasa Reddy and Subhendu Kumar Sahoo, An approach for fixed coefficient RNS-based FIR filter, International Journal of Electronics, Vol. 104 (8), 2017.

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© 2017 Centre for Software Development,SDET Unit, BITS-Pilani, India.

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