BITS Pilani

  • Page last updated on Monday, February 26, 2024

You are here:

Publications

banner
Publications

Journal Articles

#
Publication details (Reverse chronological order)
25.
Bishal Kumar Keshari, Soumi Saha, Sanghamitra Debroy, Akshay Kumar Salimath, Venkat Mattela, Subhradeep Pal, Surya Shankar Dan, Parikshit Sahatiya, "Light and Pressure Stimulated Silver Oxide (AgOx) based Memristor for In-Sensor Memory and Computing Applications", ACS Applied Electronic Materials, (Recently accepted, Jan 2024)
24.
Soumi Saha, Madadi Chetan Kodand Reddy, Tati Sai Nikhil, Kaushik Burugupally, Sanghamitra DebRoy, Akshay Salimath, Venkat Mattela, Surya Shankar Dan, and Parikshit Sahatiya, "Experimental Demonstration of SnO₂ Nanofiber-Based Memristors and their Data-Driven Modeling for Nanoelectronic Applications", Elsevier Chip, vol. 2, no. 4, Dec 2023
23.
Soumi Saha, Subhradeep Pal, Sounak Roy, Parikshit Sahatiya, and Surya Shankar Dan, "Experimental Demonstration of CeO₂-Based Tunable Gated Memristor for RRAM Applications", ACS Applied Electronic Materials, vol. 5, no. 11, pp. 6392 - 6400, Nov 2023
22.
Soumi Saha, C. J. Keerthi, Sounak Roy, Parikshit Sahatiya, Surya Shankar Dan, and Subhradeep Pal, "Engineering Oxygen Vacancies in CeO₂ for High-Performance UV-Vis Photodetector", IEEE Photonics Technology Letters, vol. 35, no. 22, pp. 1207 - 1210, Nov 2023
21.
Arun Mohan, Saroj Mondal, Surya Shankar Dan, and Roy P. Paily, "Design Considerations for Efficient Realization of Rectifiers in Micro-Scale Wireless Power Transfer Systems - A Review", IEEE Sensors Journal, vol. 23, no. 18, pp. 20691 - 20704, Sep 2023
20.
Soumi Saha, Vivek Adepu, Khush Gohel, Parikshit Sahatiya, and Surya Shankar Dan, "Demonstration of a 2D SnS/MXene Nanohybrid Asymmetric Memristor", IEEE Transactions on Electron Devices, vol. 69, no. 10, pp. 5921-5927, Oct 2022
19.
Simhadri Hariprasad and Surya Shankar Dan, "Superior Analog Performance due to Source-Gate Overlap in Vertical Line-Tunneling FETs and Their Circuits", Springer Silicon, vol. 15, pp. 117 - 126, Jul 2023
18.
Ramakant Yadav, Surya Shankar Dan, and Simhadri Hariprasad, "Low and High Vₜ GOTFET Devices Outperform Standard CMOS Technology in Ternary Logic Applications", IETE Technical Review, 39:5, pp. 1114 - 1123, Aug 2021  
DOI:10.1080/02564602.2021.1960903 (PDF)
17.
Simhadri Hariprasad, Surya Shankar Dan, Ramakant Yadav, and Ashutosh Mishra, "Double-Gate Line-Tunneling FET (DGLTFET) Devices for Superior Analog Performance", Wiley International Journal on Circuits Theory and Applications, vol. 49, issue 7, pp. 2094-2111, Apr 2021
16.
Sanjay Vidhyadharan and Surya Shankar Dan, "An Efficient Ultra-Low Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices", IEEE Transactions on Nanotechnology, vol. 20, pp. 365-376, Jan 2021
15.
Sanjay Vidhyadharan, Surya Shankar Dan, Ramakant Yadav, and Simhadri Hariprasad, "An Innovative Ultra-Low Voltage GOTFET based Regenerative-Latch Schmitt Trigger", Elsevier Microelectronics Journal, vol. 104, pp. 104879, Oct 2020 
14.
Ramakant Yadav, Surya Shankar Dan, Sanjay Vidhyadharan, and Simhadri Hariprasad, "Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices", Springer Silicon, vol. 13, pp. 1185–1197, Jul 2020
13.
Sanjay Vidhyadharan, Surya Shankar Dan, Abhay S. V., Ramakant Yadav, and Simhadri Hariprasad, "Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC", Elsevier Integration, the VLSI Journal, vol. 73, pp. 101-113, Jul 2020
12.
Sanjay Vidhyadharan, Surya Shankar Dan, Ramakant Yadav, and Simhadri Hariprasad, "A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder", Taylor and Francis International Journal of Electronics, vol. 107, no. 10, pp. 1663-1681, Mar 2020
11.
Ramakant Yadav, Surya Shankar Dan, Sanjay Vidhyadharan, and Simhadri Hariprasad, "Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node", Springer Journal of Computational Electronics, vol. 19, pp. 291-303, Jan 2020
10.
Sanjay Vidhyadharan, Ramakant Yadav, Simhadri Hariprasad, and Surya Shankar Dan, "An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications", Springer Analog Integrated Circuits and Signal Processing, vol. 102, pp. 111-123, Nov 2019 DOI:10.1007/s10470-019-01561-4 (PDF)
9.
Sanjay Vidhyadharan, Ramakant Yadav, Simhadri Hariprasad, and Surya Shankar Dan, "A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications", Springer Journal of Analog Integrated Circuits and Signal Processing, vol. 101, pp. 109-117, Jun 2019
8.
Arnab Biswas, Surya Shankar Dan, Cyril LeRoyer, Wladyslaw Grabinski, and Adrian Mihai Ionescu, "TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model", Elsevier Journal of Microelectronic Engineering, vol. 98, pp. 334-337, Oct. 2012
7.
Surya Shankar Dan, Arnab Biswas, Cyril LeRoyer, Wladyslaw Grabinski, and Adrian Mihai Ionescu, "A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction", IEEE Electron Device Letters, vol. 33, no. 2, pp. 140-142, Feb. 2012
6.
Surya Shankar Dan and Santanu Mahapatra, "Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits", IET Circuits Devices Systems, vol. 4, no. 5, pp. 449-457, Sep. 2010
5.
Surya Shankar Dan and Santanu Mahapatra, "Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits", IEEE Transactions on Nanotechnology, vol. 9, no. 1, pp. 38–45, Jan. 2010
4.
Surya Shankar Dan and Santanu Mahapatra, "Modeling and analysis of energy quantization effects on single electron inverter performance", Physica E: Low-dimensional Systems and Nanostructures, vol. 41, no. 8, pp. 1410-1416, Aug. 2009
3.
Surya Shankar Dan and Santanu Mahapatra, "Impact of Energy Quantization on the Performance of Current-Biased SET Circuits", IEEE Transactions on Electron Devices, vol. 56, no. 8, pp. 1562-1566, Aug. 2009
2.
Sitangshu Bhattacharya, Surya Shankar Dan, and Santanu Mahapatra, "Influence of band non-parabolicity on the quantized gate capacitance in δ-doped MODFED of III–V and related materials", Journal of Applied Physics, vol. 104, no. 7, p. 074304, Jul 2008 
1.
Chaitanya Sathe, Surya Shankar Dan, and Santanu Mahapatra, "Assessment of SET Logic Robustness Through Noise Margin Modeling", IEEE Transactions on Electron Devices, vol. 55, no. 3, pp. 909–915, Mar. 2008 

Conference Presentations

# Presentation details (Reverse chronological order)
20.Soumi Saha, Subhradeep Pal, Sounak Roy, Parikshit Sahatiya, and Surya Shankar Dan, "Experimental Demonstration of CeO₂-Based Tunable Gated Memristor for RRAM Applications", 37th International Conference on VLSI Design (VLSID 2024), Kolkata
19.Soumi Saha, Madadi Chetan Kodand Reddy, Tati Sai Nikhil, Kaushik Burugupally, Sanghamitra DebRoy, Akshay Salimath, Venkat Mattela, Parikshit Sahatiya, and Surya Shankar Dan, "Experimental Demonstration of SnO₂ Nanofiber-Based Memristors and their Data-Driven Modeling for Nanoelectronic Applications", 37th International Conference on VLSI Design (VLSID 2024), Kolkata
18.Anshul Awasthi, Kaushik Kalakonda, Aditi Sood, and Surya Shankar Dan, "Data-Driven ML-Assisted Modeling and Optimization of 3D FinGOTFET Device for Low-Power Yet High-Performance Digital VLSI Applications at the 10 nm Technology Node", XXIInd International Workshop on Physics of Semiconductor Devices (IWPSD 2023), Madras
17.Soumi Saha, Vivek Adepu, Parikshit Sahatiya, and Surya Shankar Dan, "Asymmetric Memresistive Switching Characteristics of p-type 2D SnS Nanomaterial", XXIInd International Workshop on Physics of Semiconductor Devices (IWPSD 2023), Madras
16.Ramakant Yadav, Surya Shankar Dan, and Ram M. Vemuri, "Analysis and Reduction of GOTFET Capacitances Using Physics-Based Compact Modeling", 27th International Symposium on VLSI Design and Test (VDAT 2023), Pilani
15. Simhadri Hariprasad and Surya Shankar Dan, "Superior Analog Performance due to Source-Gate Overlap in Vertical Line-TFETs and Their Circuits", 35th International Conference on VLSI Design (VLSID 2022), Virtual
14. Soumi Saha, Vivek Adepu, Khush Gohel, Parikshit Sahatiya, and Surya Shankar Dan, "Demonstration of a 2D SnS/MXene Asymmetric Nanohybrid Memristor", XXIst International Workshop on Physics of Semiconductor Devices (IWPSD 2021), New Delhi
13.
Simhadri Hariprasad, Surya Shankar Dan, Ramakant Yadav and Sanjay Vidhyadharan, "Innovative Strained SiGe Nanoscale Low & High VT Gate Overlap TFET Structures at 45 nm Standard CMOS Technology for Ultra-Low Power Yet High Performance Analog, Digital and Ternary VLSI Applications", XXth International Workshop on Physics of Semiconductor Devices (IWPSD 2019), Kolkata
12.
Sanjay Vidhyadharan, Ramakant Yadav, Abhay S. V., A. Krishna Shyam, Mohit P. Hirpara and Surya Shankar Dan, "An Efficient Design Approach for Implementation of 2 bit Ternary Flash ADC Using Optimized Complementary TFET Devices", 32nd International Conference on VLSI Design (VLSID 2019), New Delhi
11.
Ramakant Yadav, Sanjay Vidhyadharan, A. Krishna Shyam, Mohit P. Hirpara, Tanmay Chaudhary and Surya Shankar Dan, "Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked With Standard 45 nm CMOS Technology for Ternary Logic Applications", 32nd International Conference on VLSI Design (VLSID 2019), New Delhi
10.
Arun Mohan, Saroj Mondal and Surya Shankar Dan, "On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting", 23rd International Symposium on VLSI Design and Test (VDAT 2019), Indore
9.
Ramakant Yadav, Sanjay Vidhyadharan, Gangishetty Akhilesh, Vaibhav Gupta, Anand Ravi and Surya Shankar Dan, "Part I: Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology", XIXth International Workshop on Physics of Semiconductor Devices (IWPSD 2017), New Delhi
8.
Sanjay Vidhyadharan, Ramakant, Gangishetty Akhilesh, Vaibhav Gupta, Anand Ravi and Surya Shankar Dan, "Part II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology", XIXth International Workshop on Physics of Semiconductor Devices (IWPSD 2017), New Delhi
7.
Arnab Biswas*, Surya Shankar Dan, Cyrille Le Royer, Wladyslaw Grabinski and Adrian Ionescu, "TCAD Simulation of SOI TFETs and Calibration of non-local Band-to-Band Tunneling Model", Micro and NanoElectronic Conference, (MNE 2013), Berlin, Germany
6.
Jayita Das, Debasree Burman and Surya Shankar Dan, "A Physics-Based Compact Analytical Model for Tunnel Field Effect Transistors Based on band-to-Band Tunneling", International Conference on VLSI and Signal Processing (ICVSP 2014), Kharagpur
5.
Surya Shankar Dan and Santanu Mahapatra, "Impact of energy quantization in SET island on hybrid CMOS-SET integrated circuits", XVth International Workshop on the Physics of Semiconductor Devices (IWPSD 2009), New Delhi
4.
Surya Shankar Dan and Santanu Mahapatra, "Analysis of the energy quantization effects on single electron inverter performance through noise margin modeling", 22nd International Conference on VLSI Design (VLSID 2009), pp. 493-498, New Delhi
3.
Surya Shankar Dan and Chandan Kumar Sarkar, "Transport mechanism for Boolean logic implementation using resonant tunneling diode coupled single-electron quantum dot device", XIIIth International Workshop on the Physics of Semiconductor Devices (IWPSD 2005), Madras
2.
Madhabi Ray, Surya Shankar Dan and Chandan Kumar Sarkar, "Realization of quantum dot Boolean logic gate for image processing applications", XIIIth International Workshop on the Physics of Semiconductor Devices (IWPSD 2005), Madras
1.
Surya Shankar Dan and Saibal Pradhan, "Implementation of a 16-bit SOC microprocessor system using FPGA", International Conference on Communication, Devices Intelligent Systems (CODIS 2004), Kolkata

Doctoral Thesis Supervised

# Submission details (Reverse chronological order)
4.
Simhadri Hariprasad, "Superior Analog, Digital, and Ternary Circuit Designs Using Advanced Nano-electronic Gate Overlap Tunnel FET Devices for Ultra-Low Power Applications" (Defended in Aug 2023)(download)
Examiners:  Prof. Sudeb Dasgupta (IIT Roorkee),
                    Prof. Gaurav Trivedi (IIT Guwahati)
3.
Arun Mohan, "Energy Processing Circuits for a Multi-Band RF Energy Harvesting Systems" (Cosupervised with Dr. Saroj Mondal, Defended in Jun 2023) (download)
Examiners: Prof. Pradip Mandal (IIT Kharagpur), 
                   Prof. Prabhat Kumar Upadhyay (IIT Indore)
2.
Ramakant Yadav, "Novel Gate Overlap Tunnel FET Device Designs for Ultra-Low-Power Digital, Ternary, and Analog VLSI Applications" (Defended in Jan 2022) (download)
Examiners: Prof. Abhinav Kranti (IIT Indore),
                   Prof. Pramod Kumar Tiwari (IIT Patna)
1.
Sanjay Vidhyadharan, "Novel Gate-Overlap Tunnel FETs and Their Circuits for Ultra-Low Power VLSI Applications" (Defended in Jun 2020) (download)
Examiners: Prof. Prof. Shreepad Karmalkar (IIT Madras),
                   Prof. Tarun Kanti Bhattacharyya (IIT Kharagpur)

Book Chapters

# Publication details (Reverse chronological order)
5. Simhadri Hariprasad, Ramakant Yadav, and Surya Shankar Dan, "Novel Gate-Overlap Tunnel FETs for Superior Performance Analog, Digital and Ternary VLSI Circuit Applications Under Low-Power Consumption", CRC Press (https://doi.org/10.1201/9781003359234-4)(download)
4. Sanjay Vidhyadharan and Surya Shankar Dan, "Gate-Overlap Tunnel Field- Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications", Chapter 8, Taylor & Francis, (https://doi.org/10.1201/9781003168225-8)(download)
3.
Arun Mohan, Saroj Mondal and Surya Shankar Dan, "On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting", Springer VLSI Design and Testing, vol. 1066, A. Sengupta, S. Dasgupta, V. Singh, R. Sharma, and S. Kumar Vishvakarma, Eds. Singapore: Springer Singapore, 2019, pp. 180–189, Aug 2019, (https://doi.org/10.1007/978-981-32-9767-8_16) (download)
2.
Sanjay Vidhyadharan, Ramakant Yadav, Gangishetty Akhilesh, Vaibhav Gupta, Anand Ravi and Surya Shankar Dan, "Part II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology", Springer Physics of Semiconductor Devices, vol. 215, R. K. Sharma and D. S. Rawal, Eds. Cham: Springer International Publishing, 2019, vol. 215, pp. 619–628, Feb 2019, (https://doi.org/10.1007/978-3-319-97604-4_96) (download)
1.
Ramakant Yadav, Sanjay Vidhyadharan, Gangishetty Akhilesh, Vaibhav Gupta, Anand Ravi and Surya Shankar Dan, "Part I: Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology", Springer Physics of Semiconductor Devices, vol. 215, R. K. Sharma and D. S. Rawal, Eds. Cham: Springer International Publishing, 2019, vol. 215, pp. 611–618, Feb 2019, (https://doi.org/10.1007/978-3-319-97604-4_95) (download)

Quick Links

    An Institution Deemed to be University estd. vide Sec.3 of the UGC Act,1956 under notification # F.12-23/63.U-2 of Jun 18,1964

    © 2024 Centre for Software Development,SDET Unit, BITS-Pilani, India.

    Designed and developed by fractal | ink design studios