1. Pranshu, Shaishta, Nitin, S Gurunarayanan, “An Exploration of Neuromorphic Systems and Related Design Issues/Challenges in Dark Silicon Era” in 3rd International Conference on Communication Systems, ICCS-2017, 14-16 October 2017, Pilani, India.
2. Suvi Jain, Nitin Chaturvedi, S Gurunarayanan, “Design and Analysis of 6T SRAM Cell with NBL Write Assist Technique Using FinFET” in International Conference on Computer, Communications and Electronics, COMPTELIX 2017, 1-2 July 2017,Jaipur,India .(IEEE-Xplore)
3. Divya Suneja, Nitin Chaturvedi, S Gurunarayanan, “A Comparative Analysis of Read/Write Assist Techniques on Performance & Margin in 6T SRAM Cell Design” in International Conference on Computer, Communications and Electronics, COMPTELIX 2017, 1-2, July 2017, Jaipur, India (IEEE -Xplore)
4. Nikunj, Nitin Chaturvedi, S Gurunarayanan, “Design Of Non-Volatile Asynchronous Circuit Using CMOS-FDSOI/FinFET Technologies” in IEEE International Conference on Computing, Analytics and Security Trends, CAST-2016, 19-21 December 2016, Pune, India (IEEE-Xplore)
5. Pranshu, Shaishta, Nitin Chaturvedi, S Gurunarayanan, “An Investigation of Power- Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems” in 2nd IEEE International symposium on nanoelectronic and information systems, IEEE-INIS-2016, 19-21 December 2016, IIITM Gwalior,India (IEEE-Xplore)
6. GSS Chalapathi, R. Manekar, V. Chamola, K.R. Anupama and S Gurunarayanan, "Hardware
Validated Efficient Simple Time Synchronization Protocol for clustered WSN," IEEE TENCON, 2016, Singapore, Nov. 22- 25, 2016.
7. R. Manekar, GSS Chalapathi, V. Chamola, K.R. Anupama and S Gurunarayanan,
“A Simple Time Synchronization Algorithm for WSNs in Smart Grid Applications,”
IEEE Symposium on Emerging Topics in Smart and Sustainable Grids, Singapore, Sept. 2016
8. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, An Embedded Frame work
for Accurate Object Localization using Center of Gravity Measure with Mean Shift Procedure, IEEE 19th International Symposium on VLSI Design and Test,
Ahmedabad, India, 26-29 June 2015, pp. 1-6.
8.
9. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “Architectures for Embedded Vision Application using FPGA-based Platform” IEEE 28th Int’l Conf. on VLSI Design and 14th Int’l Conf. on Embedded Systems (VLSI Design 2015), Bangalore, India, 3-7 Jan. 2015.
10. J.G. Pandey, A Karmakar, C Shekhar, S Gurunarayanan, “An FPGA-based architecture for local similarity measure for image/video processing applications” 2015, 28th International Conference on VLSI Design, 339-344, Bangalore, India.
11. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, Architectures and algorithms for image and video processing using FPGA-based platform IEEE 18th International Symposium on VLSI Design and Test, Coimbatore, India,16-18 July 2014 pp.1-1
12. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “A novel architecture for FPGA implementation of Otsu’s global automatic image thresholding algorithm,” in Proceedings of IEEE 27th International Conf. on VLSI Design and 13th International Conf. on Embedded Systems (VLSI Design 2014), Mumbai, India, 5-9 Jan. 2014, pp. 300-305. (IEEE Xplore) [Impact factor: 0.40] (For Year 2012)
13. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based architecture for kernel-smoothed local histogram computation,”Accepted for publication in IEEE International Symposium on Circuits and Systems (ISCAS-2014), Melbourne, Australia, 01-05 June, 2014. (IEEE - Xplore) [Impact factor: 0.27] (For Year 2012).
14. J. G. Pandey, A. Karmakar, A. K. Mishra, C. Shekhar, and S. Gurunarayanan, “Implemention of an improved connected component labeling algorithm using FPGA based platform,” Accepted for Publication in IEEE International Conf. on Signal Processing and Communications (SPCOM, 2014), IISc-Bangalore, India, 22-25 July 2014. (IEEE- Xplore)
15. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based novel architecture for the fixed-point binary antilogarithmic computation,” in Proceedings of IEEE International Conf. on Electronic Systems, Signal Processing and Computing Technologies (ICESC), Nagpur, India, 09-11 Jan. 2014, pp. 23-28. (IEEE- Xplore) [Best Paper Award]
. 16. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based
fixed-point architecture for binary logarithmic computation,” in
Proceedings of 2nd IEEE International Conf. in Image Information Processing (ICIIP-2013),
Shimla, India, 09-12 Dec. 2013, pp. 383- 388. (IEEE -Xplore)
17. Nitin Chaturvedi, S Gurunarayanan, “An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-Core Architectures” 2013 IEEE International Conference on Computational Intelligence and Communication Network, ICCN- 2013, September 27-29, 2013, Mathura, India (IEEE –Xplore)
18. Nitin Chaturvedi, S Gurunarayanan, “An Adaptive Cache Coherence Protocol with adaptive Cache for Multi-core Architectures” in proceedings of International Conference on Advanced Electronic Systems, ICAES-2013 September 21-23, 2013, CEERI, Pilani,India (IEEE –Xplore)
19. Munish Bhathia, D.C.Kiran, S Gurunarayanan, and J.P.Misra, "Fine Grain Thread Scheduling on Multicore Processors: Cores With Multiple Functional Units". Compute '13: Proceedings of the 6th ACM India Computing Convention, Vellore, Tamilnadu, India. August 2013 Article No.: 20 Pages 1–6 . https://doi.org/10.1145/2522548.2523137. http://dl.acm.org/citation.cfm? doid=2522548.2523137
20. D.C. Kiran, S. Gurunarayanan, J.P.Misra, and D.Yashas "Integrated Scheduling and Register Allocation For Multicore Architecture". In IEEE Conference on Parallel Computing Technologies PARCOMPTECH-2013, Organized by C-DAC in IISC Bangalore, February 2013. https://ieeexplore.ieee.org/document/6621400
21. D.C. Kiran, S. Gurunarayanan, and J.P.Misra, Compiler Driven Inter Block Parallelism for Multicore Processors. In 6th International Conference on Information Processing, published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, Bangalore, India, August 2012. http://link.springer.com/chapter/10.1007/978-3-642-31686-9_50
22. D.C. Kiran, S. Gurunarayanan, Faizan Khaliq, and Abhijeet Nawal, Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architectures. In The International Conference of Eco-friendly Computing and Communication Systems, (ICECCS) 2012, Kochi, India, August 9-11, 2012. Proceedings published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, pp.9-17 http://link.springer.com/chapter/10.1007%2F978-3-642-32112-2_2
23. D.C. Kiran, S. Gurunarayanan, J.P.Misra and Faizan Khaliq, An Efficient Method to Compute Static Single Assignment Form for Multicore Architecture. In 1st IEEE International Conference on Recent Advances in Information Technology, Dhanbad, India. March, 2012. pp. 776-789, http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6194553
24. Nitin Chaturvedi, Prashant Gupta, S Gurunarayanan, “Efficient Cache Migration Policy for Chip Multi-Processors” 2011 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC-11, 15-18 December 2011. Kanyakumari, Tamilnadu, India.
25. D.C. Kiran, S. Gurunarayanan, and J.P.Misra, Taming Compiler to Work with Multicore Processors. IEEE Conference on Process Automation, Control and Computing. Coimbatore, Tamilnadu, India 20-22 July 2011. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5978868
26. D.C.Kiran, B. Radheshyam. Gurunarayanan, and J.P.Misra, Compiler Assisted Dynamic Scheduling for Multicore Processors. IEEE Conference on Process Automation, Control and Computing, Coimbatore, Tamilnadu, India, July,20- 22, 2011. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5978903
27. Nitin Chaturvedi, Pradeep Harinderan, S Gururnarayanan, “A Novel shared L2 NUCA cache partitioning scheme for Multi-core Architectures” in proceedings of International Conference on Emerging Trends in Engineering (ICETE),Maharashtra, India, Feb.20-21, 2010. pp. 183-188.
28. Biju Raveendran , Sundar Balasubramaniam , and S. Gurunarayanan. “Evaluation of Priority Based Real Time Scheduling Algorithms: Choices and Tradeoffs.” In Proceedings of the 23rd Annual ACM Symposium on Applied Computing (ACM SAC'08), Brazil, Mar-2008, vol. 1, pp. 302 - 307.
29. Biju Raveendran, T S B Sudarshan, Avinash Patil, Komal Randive, and
S Gurunarayanan. “Predictive Placement Scheme for Set-Associative Cache for Energy Efficient Embedded System.” Proceedings of International Conference on Signal Processing, Communications and Networking, (ICSCN 2008),January 4-6, 2008, Chennai,
Tamilnadu, India pp. 152-157, Available online in IEEEXPLORE.
30. Biju Raveendran, T S B Sudarshan, Dlip Kumar, Priyanaka Tugudu and S Gurunarayanan. “LLRU: Late LRU Replacement Strategy for Power Efficient Embedded Cache.”Proceedings of 15th IEEE International Conference On Advanced Computing (ADCOM), IIT-Kharagpur,India Dec-2007, pp. 339-344, Available online in IEEEXPLORE.
31. Biju Raveendran, T S B Sudarshan, Avinash Patil, Komal Randive, and S Gurunarayanan. “An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System.” Proceedings of ESA'07- The 2007 International Conference on Embedded Systems and Applications, USA, (Published by CSREA Press, Jun-2007, pp. 188–194.
32. Biju Raveendran, J P Misra, Karan Bhatnagar and S Gurunarayanan. “EFFS: Efficient Flash File System for Wireless Sensor Nodes.” Proceedings of ESA'07- The 2007 International
Conference on Embedded Systems and Applications, USA, (Published by CSREA Press,
Jun-2007, pp. 159– 165.
33. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Selective Placement Data Cache for Low Energy Embedded System”. Proceedings of 14th IEEE International Conference On Advanced Computing (ADCOM), NITK, Surathkal, India. Dec-20-23, 2006, pp. 473-476, Available online in IEE-EXPLORE.
34. Ninad B Kothari, T S B Sudarshan, S Gurunarayanan, and S Chandrashekhar. “SoC Design of a Low Power Wireless Sensor Network Node for Zigbee Systems.” Proceedings of 14th IEEE International Conference On Advanced Computing (ADCOM), NITK, Surathkal, India. Dec- 20-23-2006, pp. 462-466. Available online in IEE-EXPLORE.
35. Biju Raveendran , Sundar Balasubramaniam , K Durga Prasad and S. Gurunarayanan. “Variants of Priority Scheduling Algorithms for Reduced Context Switches in Real Time System.” 8th International Conference on Distributed Computing and Networking (ICDCN), Lecture Notes in Computer Science, Springer-Verlag. IIT - Guwahati, India. Dec-2006, pp. 466-478.
36. Biju Raveendran , Sundar Balasubramaniam , K Durga Prasad and S. Gurunarayanan. “A Context- Switch Reduction Heuristic for Power-Aware Off-line Scheduling.” 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC), Lecture Notes in Computer Science, Vol. 4186, Springer-Verlag. Shanghai, China, Sep-2006, pp. 404-411.
37. Ninad B Kothari, T S B Sudarshan, Shipra Bhal, Tejesh E C, and S Gurunarayanan. “Design of an Efficient Low-Power AES Engine for Zigbee Systems.” Proceedings of 10th IEEE VLSI Design & Test Symposium (VDAT), Goa, India. Aug-2006, pp. 264-272.
38. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Cache Memory Design with Late Replacements for Embedded Systems.” Proceedings of 2nd International Conference on Embedded Systems, Mobile Communication and Computing (ICEMC2), Bangalore, India. Aug- 2006, pp. 76- 90.
39. Gurunarayanan , R Mehrotra and S Chandrashekhar. “Modelling of ESD Protection Circuits.”Proceedings of 8th International Workshop on Physics of Semiconductor
Devices, New Delhi, India. 1995.
40. Gurunarayanan , R Mehrotra and S Chandrashekhar.”Drain Induced Barrier lowering in short channel NMOS Devices.”Proceedings of 7th International Workshop on Physics of Semiconductor Devices. New Delhi, India Dec. 14-18, 1993. 75-76. Narosa Publishing House, 1994