BITS Pilani

  • Page last updated on Sunday, January 16, 2022

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Profile

Dr. Amit Kumar Panda

Assistant Professor
 
 
Contact Details:

 
Department of EEE,
Room No. - H-204
BITS Pilani Hyderabad Campus
Jawahar Nagar, Hyderabad, Telangana - 500 078
 
Email: amit@hyderabad.bits-pilan.ac.in
Phone: +91-40-66303-746
 
 

Professional Experience:

  • Assistant Professor: BITS Pilani Hyderabad Campus (Jan' 20 – present)
  • Senior Research Fellow: IIT Patna (Sep' 13 – Jan' 20)
  • Assistant Professor: Central University of Jharkhand (Aug, 12 - Sep' 13)
  • Assistant Professor: Guru Ghasidas (Central) University (Sep' 09 – Apr' 12)
 

Educational:

  • Ph.D.:Electrical Engineering, IIT Patna, Jan 2020
  • M.Tech. (Electronics Des. & Tech): Tezpur Central University, Assam, 2009
  • M.Sc. (Electronics): Berhampur University, Odisha, 2004
 
About the Faculty:
Dr Amit Kumar Panda has received the M.Sc. degree in electronics from Berhampur University, India, in 2004, then M. Tech. degree in Electronic Design and Technology from Tezpur Central University, India, in 2009 and Ph.D. degree in Electrical Engineering from Indian Institute of Technology Patna. He served as an Assistant Professor with the Electronics and Communication Engineering Department, Guru Ghasidas Vishwavidyalaya, India, from 2009 to 2012. He was an Assistant Professor with the Centre for Nanotechnology, Central University of Jharkhand, India, from 2012 to 2013.
 
His research interests include VLSI architectural design, FPGA based system design, VLSI architecture of Pseudorandom bit/number generation, VLSI cryptography and Hardware Security. He has good exposer in FPGA prototype, debugging with Xilinx Chipscope and logic analyzer, RTL design using Xilinx (ISE, System generator, IP core, Vivado) and Synposys (DC compiler, IC compiler). He has developed highly random and secured LCG-based PRBG methods such as Modified dual-CLCG and CVLCG, and their efficient VLSI architectures for stream cipher applications. He has also developed the efficient architecture of Blum-Blum-Shub (BBS) which is a polynomial time unpredictable, cryptographically secured PRBG method. He has worked on the arithmetic circuits such as adder, multiplier and comparator for the efficient implementation of random key generators, cryptography algorithms, physical security for the next generation communication system. He is currently working in light weight cryptographic processor for IoT applications.
 
 
  • I am looking a highly motivated student who has the good exposer in VLSI Architectural Design, Hardware Security, VLSI for Cryptography and FPGA based system design, etc. for full time Institute fellowship PhD.
  • Those who have their own fellowship such as UGC, CSIR and any other are highly encourage to contact me for Full-Time PhD.
 

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