BITS Pilani

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Publications

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Publications

Publications

Journals Papers:

  1. R. Palisetty, A. K. Panda and K. C. Ray, “ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah,” in IEEE Transactions on Instrumentation and Measurement, vol. 70, pp. 1-10, 2021, Art no. 2002810, doi: 10.1109/TIM.2020.3045809. (Impact Factor: 3.658) Link
  2. A. K. Panda, R. Palisetty and K. C. Ray, “High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 3944-3953, Nov. 2020, doi: 10.1109/TCSI.2020. (Impact Factor: 3.318) Link
  3. A. K. Panda and K. C. Ray, “A Coupled Variable Input LCG Method and its VLSI Architecture for Pseudorandom Bit Generation,” in IEEE Transactions on Instrumentation and Measurement, vol. 69, no. 4, pp. 1011-1019, April 2020, doi: 10.1109/TIM.2019.2909248. (Impact Factor: 3.658) Link
  4. A. K. Panda and K. C. Ray, “Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 3, pp. 989-1002, March 2019, doi: 10.1109/TCSI.2018.2876787. (Impact Factor: 3.318) Link

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