Abroad:
1.
Reddy, C. Sai Revanth, U. Anil Kumar, and. Syed Ershad Ahmed, "Design of Efficient Approximate Multiplier for Image Processing Applications," In International conference on Modelling, Simulation and Intelligent Computing, pp. 511-518. Springer, Singapore, 2020. (Presented in BITS Pilani Dubai)2. Syed Ershad Ahmed, Sanket Kadam, and M. B. Srinivas, "An iterative logarithmic multiplier with improved precision." 2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH). IEEE, 2016, Silicon Valley, CA, USA, 2016
3.
Syed Ershad Ahmed and M. B. Srinivas, "Design of Low Power MAC unit in High Performance DSP Systems
." 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
, Istanbul, Turkey, 2013
India:
1. Alla, Navteja, and Syed Ershad Ahmed, "An Area and Delay Efficient Logarithmic Multiplier," In 2020 International Conference on Contemporary Computing and Applications (IC3A), pp. 169-174. IEEE,AKTU, Lucknow, 2020
2. Syed Ershad Ahmed, S. Sweekruth Srinivas, and M. B. Srinivas. "A Hybrid Energy Efficient Digital Comparator." 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID). IEEE, Kolkata, 2016.
3.Varma, Ch, Syed Ershad Ahmed and M. B. Srinivas. "A Decimal/Binary Multi-operand Adder Using aFast Binary to Decimal Converter." VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on. IEEE, Mumbai, 2014.
4. K.V.S.Sashank , Syed Ershad Ahmed , " A Reconfigurable Fixed Width Scheme for Recursive Multipliers”, Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2013 , 19-21,Visakhapatnam, Dec. 2013.
5.Ganguly, Soumya, Abhishek Mittal, and Syed Ershad Ahmed, "A Reconfigurable Parallel Prefix Ling Adder with modified Enhanced Flagged Binary logic." Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in. IEEE, Hyderabad, 2012.
6.Ahmed, Syed Ershad, Sibi Abraham, Sreehari Veeramanchaneni, and M. B. Srinivas. "A modified twin precision multiplier with 2D bypassing technique." In 2012 International Symposium on Electronic System Design (ISED), pp. 102-106. IEEE, Kolkata,2012.
7..Kumar, V. Chetan, P. Sai Phaneendra, Syed Ershad Ahmed, V. Sreehari, N. Moorthy Muthukrishnan, and M. B. Srinivas. "A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block." In 2011 International Symposium on Electronic System Design, pp. 100-105. IEEE, Kochi, 2011.