Journals:
13.
Sahith, U. Anil Kumar, Vignesh and Syed Ershad Ahmed. "Design Methodology for Highly Accurate Approximate Multiplier for Error Resilient Applications," Computers and Electrical Engineering (2023). [Accepted] 12. U. Anil Kumar, Vignesh and Syed Ershad Ahmed. "Compressor based Hybrid Approximate Multiplier Architectures with Efficient Error Correction Logic," Computers and Electrical Engineering (2022). [Accepted]
11. U. Anil Kumar, Sahith and Syed Ershad Ahmed. "Design and Exploration of Low Power SAD Architectures using Approximate Compressors for Integer Motion Estimation," Microprocessor and Microsystem (2022). [Accepted]
10. U. Anil Kumar, Avinash, Vignesh, Suresh and Syed Ershad Ahmed. "CAAM: Compressor-based Adaptive Approximate Multipliers for Neural Network Applications ," IEEE Embedded Systems Letters (2022). [Accepted]
9. Aroondhati, Smriti, U. Anil Kumar, and Syed Ershad Ahmed, "A General Methodology to Optimize Flagged Constant Addition ,"Journal of Circuits, Systems and Computers (2022) [Accepted]
8. U. Anil Kumar, Sumit Kumar and Syed Ershad Ahmed. "Low-Power Compressor-based Approximate Multipliers with Error-Correcting Module ," IEEE Embedded Systems Letters (2021).
7. Syed Ershad Ahmed and Mohan, "An Efficient Hardware Approach for Approximate Logical Computation ,"Journal of Circuits, Systems and Computers (2021)
6. U. Anil Kumar, Sahith, Sumit Chatterjee, and Syed Ershad Ahmed, "A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications ,"Journal of Circuits, Systems and Computers (2021).
5. Nambi, Suresh, U. Anil Kumar, Kavya Radhakrishnan, Mythreye Venkatesan, and Syed Ershad Ahmed. "DeBAM: Decoder Based Approximate Multiplier for Low Power Applications," IEEE Embedded Systems Letters (2020).
4. U. Anil Kumar and Syed Ershad Ahmed, " Hardware Efficient Approximate Multiplier Architectures for Media Processing Applications,” Circuit World. (2021)
3. U. Anil Kumar and Syed Ershad Ahmed, "Compressor based Approximate Multiplier Architectures for Media Processing Applications,” International Journal of Electrical & Computer Engineering, Vol 11, No.4, Aug 2021
2. Syed Ershad Ahmed and M. B. Srinivas, "An improved logarithmic multiplier for media processing." Journal of Signal Processing Systems (2019): 561-574
1.Syed Ershad Ahmed, Santosh Varma, and M. B. Srinivas, "Improved designs of digit-by-digit decimal multiplier." Integration 61 (2018): 150-159.
Book Chapter:
1. U. Anil Kumar, and. Syed Ershad Ahmed, "A Classification and Evaluation of Approximate Multipliers," In Microelectronics and Signal Processing Advanced Concepts and Applications,1st Edition, CRC Press, Taylor & Francis (2021).
Conferences:
2023:
1. Anil Kumar, Kudari Shreya, Babitha, Srihari and. Syed Ershad Ahmed, " Low-
Power Approximate Adder Architecture for Image Processing Applications”, 2023, I3CS (Accepted)
2022:
11 1. Suraj, Naren, Anil Kumar and. Syed Ershad Ahmed, " Power Efficient Approximate Booth Multipliers for Error Resilient Applications”, 2022 INDICON (Accepted)
2. Anil Kumar, Sreehari and. Syed Ershad Ahmed, “Power Efficient Approximate Multiplier Architectures for Error Resilient Applications”, 2022 INDICON (Accepted)
3. Sriram, Anil Kumar and. Syed Ershad Ahmed, " Power Efficient Approximate Divider Architectures for Error Resilient Applications”, 2022 IEEE CICT Accepted)
2021:
11 1. Santhosh and. Syed Ershad Ahmed, "Design and Evaluation of Efficient Decimal Multiplier Architectures," In Soft Computing and Signal Processing, pp. 563-571. Springer, Singapore, 2021.
2. Anil Kumar and. Syed Ershad Ahmed, "Approximate Multiplier Architectures for Error Resilient Applications:, 2021 IEEE International Symposium on Smart Electronic Systems (Accepted)
3. Sahith, Anil Kumar and. Syed Ershad Ahmed, "Power Efficient MLOA for Error Resilient Applications:, 2021 IEEE International Symposium on Smart Electronic Systems (Accepted)
4. Anil Kumar and. Syed Ershad Ahmed, "Lower part OR Based Approximate Multiplier for Error Resilient Applications:, 2021 IEEE International Symposium on Smart Electronic Systems (Accepted)
5.
Syed Ershad Ahmed et al. "Face Recognition and Detection using Inexact Arithmetic, 2021 IEEE ICONAT (Accepted)
2020:
1. 1.Reddy, C. Sai Revanth, U. Anil Kumar, and Syed Ershad Ahmed, "Design of Efficient Approximate Multiplier for Image Processing Applications," In International conference on Modelling, Simulation and Intelligent Computing, pp. 511-518. Springer, Singapore, 2020.
2. 2. Alla, Navteja, and Syed Ershad Ahmed, "An Area and Delay Efficient Logarithmic Multiplier," In 2020 International Conference on Contemporary Computing and Applications (IC3A), pp. 169-174. IEEE, 2020
3. 3. Kumar, Uppugunduru Anil, Nishant Jain, Sumit K. Chatterjee, and Syed Ershad Ahmed,"Evaluation of Multiplier-Less DCT Transform Using In-Exact Computing," In International Conference on Machine Learning, Image Processing, Network Security and Data Sciences, pp. 11-23. Springer, Singapore, 2020.
4. 4. Kumar, Uppugunduru Anil, Mohammed Hamed Ahmed, and Syed Ershad Ahmed, "An Evaluation of the Canny Edge Detection Algorithm using Hybrid Approximate Adder Architecture," In 2020 IEEE-HYDCON, pp. 1-5. IEEE, 2020.
5
2016:
1. Syed Ershad Ahmed, Sanket Kadam, and M. B. Srinivas. "An iterative logarithmic multiplier with improved precision." 2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH). IEEE, 2016.
2. Syed Ershad Ahmed, S. Sweekruth Srinivas, and M. B. Srinivas. "A Hybrid Energy Efficient Digital Comparator." 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID). IEEE, 2016.
2014:
1. Soumya Ganguly, Abhishek Mittal,
Syed Ershad Ahmed and M.B.Srinivas. "A Unified Flagged Prefix Constant Addition-Subtraction Scheme for Design of Area and Power Efficient Binary Floating-Point and Constant Integer Arithmetic Circuits."
IEEE Asia Pacific Conference on Circuits and Systems(APCCAS),2014, 17-20 Nov.2014, Ishigaki Island, Okinawa, Japan.
2. Varma, Ch, Syed Ershad Ahmed and M. B. Srinivas. "A Decimal/Binary Multi-operand Adder Using aFast Binary to Decimal Converter." VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on. IEEE, 2014.
2013:
1. K.V.S.Sashank , Syed Ershad Ahmed , " A Reconfigurable Fixed Width Scheme for Recursive Multipliers”, Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2013 , 19-21 Dec. 2013.
2. Syed Ershad Ahmed and M.B.Srinivas , "Design of Low Power MAC unit in High Performance DSP Systems, “21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) , proceedings., 7-9 October 2013, Istanbul ,Turkey.
3. Syed Ershad Ahmed, Pawan Sastry, Sreehari Veeramanchaneni, M.B.Srinivas;, " A High Accuracy, Low Memory Logarithmic Converter “,Fourth International Symposium Highly-Efficient Accelerators and Reconfigurable Technologies (HEART) , conference proceedings., pp.121-124, 13-14 June 2013,Edinburgh ,Scotland.
2012:
1.Ganguly, Soumya, Abhishek Mittal, and Syed Ershad Ahmed, "A Reconfigurable Parallel Prefix Ling Adder with modified Enhanced Flagged Binary logic." Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in. IEEE, 2012.
2.Vudadha, Chetan, Syed Ershad Ahmed et al. "Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders." 2012 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2012.
3. Vudadha, Chetan, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, and M. B. Srinivas. "Low-power self reconfigurable multiplexer based decoder for adaptive resolution flash adcs." In 2012 25th International Conference on VLSI Design, pp. 280-285. IEEE, 2012.
4.6.Ahmed, Syed Ershad, Sibi Abraham, Sreehari Veeramanchaneni, and M. B. Srinivas. "A modified twin precision multiplier with 2D bypassing technique." In 2012 International Symposium on Electronic System Design (ISED), pp. 102-106. IEEE, 2012.
2011:
1. Kumar, V. Chetan, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, and M. B. Srinivas. "A unified architecture for BCD and binary adder/subtractor." In 2011 14th Euromicro Conference on Digital System Design, pp. 426-429. IEEE, 2011.
2.Kumar, V. Chetan, P. Sai Phaneendra, Syed Ershad Ahmed, V. Sreehari, N. Moorthy Muthukrishnan, and M. B. Srinivas. "A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block." In 2011 International Symposium on Electronic System Design, pp. 100-105. IEEE, 2011.
3.Kumar, Chetan, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, and M. B. Srinivas. "A prefix based reconfigurable adder." In 2011 IEEE Computer Society Annual Symposium on VLSI, pp. 349-350. IEEE, 2011.