BITS Pilani

  • Page last updated on Sunday, January 29, 2023

You are here:

  • Home
  • Doctoral Thesis

Sanjay Vidhyadharan - Doctoral Thesis

banner
Assistant Professor

  • Title : ‘Novel Gate Overlap Tunnel FET based Ultra-Low Power VLSI Circuits as a viable alternative to CMOS Technology’.
  • Supervisor : Dr. Surya Shankar Dan
  • Institute : BITS Pilani, Hyderabad Campus.
  • Status : Completed Jan 2020.

Quick Links

    An Institution Deemed to be University estd. vide Sec.3 of the UGC Act,1956 under notification # F.12-23/63.U-2 of Jun 18,1964

    © 2024 Centre for Software Development,SDET Unit, BITS-Pilani, India.

    Designed and developed by fractal | ink design studios