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Sanjay Vidhyadharan - Publications

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Assistant Professor

 
Journals  /  Book Chapters
 
2022
 
21.     Abhay S. Vidhyadharan, Aiswarya Satheesh, Kilari Pragnaa & Sanjay Vidhyadharan, “ High-Speed and Area-Efficient CMOS and CNFET-Based Level-Shifters” Circuits, Systems, and Signal Processing  https://doi.org/10.1007/s00034-022-01999-4
 
20.  Abhay S. Vidhyadharan, Sanjay Vidhyadharan, “ CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications” Wireless Personal Communications,

https://doi.org/10.1007/s11277-021-09135-2

2021
 
 
19. Sanjay Vidhyadharan and SS Dan “ Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications “ Microelectronics and Signal Processing Chapter 8 pages 137-164 CRC Press June 7, 2021. 
 
18.  Abhay S. Vidhyadharan, Sanjay Vidhyadharan, “Memristor–CMOS hybrid ultra-low-power high-speed multivibrators.,” Springer Analog Integrated Circuits and Signal Processing, 2021, DOI: 10.1007/s10470-021-01856-5.
URL: https://link.springer.com/article/10.1007/s10470-021-01856-5
 
 17.  Abhay S. Vidhyadharan, Sanjay Vidhyadharan, “Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs,” International Journal of Electronics, 2021, doi = 10.1080/00207217.2021.1908616,  URL = https://doi.org/10.1080/00207217.2021.1908616
 
 16.  Abhay S. Vidhyadharan, Sanjay Vidhyadharan, “A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM,” Microelectronics Journal, Volume 111, 2021, 105033,ISSN 0026-2692, https://doi.org/10.1016/j.mejo.2021.105033.
 
 
 15.  Vidhyadharan, A.S. and Vidhyadharan, S. (2021), "Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications", World Journal of Engineering, Vol. ahead-of-print No. ahead-of-print. https://doi.org/10.1108/WJE-08-2020-0367
 
 
 14.  Abhay S. Vidhyadharan, Sanjay Vidhyadharan, “An Ultra-Low-Power CNFET based Improved Schmitt Trigger Design for VLSI Sensor Applications”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields. https://onlinelibrary.wiley.com/doi/epdf/10.1002/jnm.2874
 
 13.  Abhay S. Vidhyadharan, Kasthuri Bha & Sanjay Vidhyadharan, “CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder”  Springer Circuits, Systems, and Signal Processing. https://link.springer.com/article/10.1007/s00034-021-01664-2
 
 
12.   S. Vidhyadharan and S. S. Dan “An Efficient Ultra-Low Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices” IEEE Transactions on Nano Technology. DOI 10.1109/TNANO.2020.3049087. https://ieeexplore.ieee.org/document/9314093.
 
11. Abhay S. Vidhyadharan, Sanjay Vidhyadharan, An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder, Microelectronics Journal, Volume 107, 2021, 104961, ISSN 0026-2692, 
https://doi.org/10.1016/j.mejo.2020.104961. (http://www.sciencedirect.com/science/article/pii/S0026269220305607)
 
 2020 
 
10.   Abhay SV,  S. Vidhyadharan, “TiO2−x–TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node”,  Springer Transactions on Electrical and Electronic Materials, October 2020. https://doi.org/10.1007/s42341-020-00253-5 . https://doi.org/10.1007/s42341-020-00253-5 
 
 9. S. Vidhyadharan , R. Yadav, S. Hariprasad, and S. S. Dan, “An Innovative Ultra-Low Voltage GOTFET based Regenerative-Latch Schmitt Trigger”, Microelectronics Journal, Volume 104, October 2020, https://doi.org/10.1016/j.mejo.2020.104879.
 
 8. R. Yadav, S. S. Dan, S. Vidhyadharan , and S. Hariprasad, “Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor,” Springer Silicon. Jul 2020. https://doi.org/10.1007/s12633-020-00506-1
 
7. R. Yadav, S. S. Dan, S. Vidhyadharan , and S. Hariprasad, “An innovative multi-threshold gate-overlap tunnel fet (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45 nm technology node.for low power VLSI applications,” Springer Journal of Computational Electronics. Vol 19, pp-291-303. DOI: 10.1007/ s10825-019-01440-1. https://link.springer.com/article/10.1007/s10825-019-01440-1
 
 6. S. Vidhyadharan , S. S. Dan , Abhay S,V,  R. Yadav and S. Hariprasad,, “Novel Gate-Overlap Tunnel FET based Innovative Ultra-Low Power Ternary Flash ADC”, Integration: The VLSI Journal, Vol.73C, pp101-113 https://doi.org/10.1016/j.vlsi.2020.03.006
 
5.  S. Vidhyadharan , S. S. Dan,  R. Yadav, and S. Hariprasad,, “A Novel Ultra-Low Power Gate-Overlap Tunnel FET (GOTFET) Dynamic Adder”, Taylor & Francis Journal of Electronics. DOI: 10.1080/00207217.2020.1740800. Vol. 107, Issue 10. 2020  https://doi.org/10.1080/00207217.2020.1740800. 
https://www.tandfonline.com/doi/full/10.1080/00207217.2020.1740800
 
 
 2019
 
4.  S. Vidhyadharan , R. Yadav, S. Hariprasad, and S. S. Dan, “An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications”, Springer Analog Integrated Circuits and Signal Processing, 2020, Vol. 102, pp-111-123. DOI:10.1007/s10470-019-01561-4.  
https://link.springer.com/article/10.1007/s10470-019-01561-4 
  
3. S. Vidhyadharan , R. Yadav, S. Hariprasad, and S. S. Dan, “A Nanoscale Gate-Overlap Tunnel FET (GOTFET) Based Improved Double Tail Dynamic Comparator for Ultra-Low-Power VLSI Applications”, Springer Analog Integrated Circuits and Signal Processing, Vol.101, pp-109-117, 2019. DOI:10.1007/ s10470-019-01487-x  https://link.springer.com/article/10.1007/s10470-019-01487-x
 
2. R. Yadav, S. Vidhyadharan, G. Akhilesh, V. Gupta, A. Ravi, and S. S. Dan, “Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology," in The Physics of Semiconductor Devices, R.K. Sharma and D. Rawal, Eds. Springer International Publishing, 2019, Vol. 215, Chapter 95, pp. 611-618. [Online]:  https://link.springer.com/chapter/10.1007/978-3-319-97604-4_95
 
1. S. Vidhyadharan, R. Yadav, G. Akhilesh, V. Gupta, A. Ravi, and S. S. Dan, “Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology," in The Physics of Semiconductor Devices, R. K. Sharma and D. Rawal, Eds. Springer International Publishing, 2019, Vol. 215, Chapter 96, pp. 619-628. [Online]:  https://link.springer.com/chapter/10.1007/978-3-319-97604-4_96
  
Conferences
 
1. S. Vidhyadharan, R. Yadav, G. Akhilesh, V. Gupta, A. Ravi, and S. S. Dan, “Part-II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology," 19th International Workshop on Physics of Semiconductor Devices (IWPSD 2017), Delhi.
 
2. R. Yadav, S.Vidhyadharan, G.Akhilesh, V.Gupta, A.Ravi, and S.S.Dan, “Part-I: Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology," in 19th International Workshop on Physics of Semiconductor Devices (IWPSD 2017), Delhi.
 
3. S. Vidhyadharan, R. Ramakant, A. S. Vidhyadharan, A. K. Shyam, M. P. Hirpara, and S.S. Dan, "An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADCUsing Optimized Complementary TFET Devices," 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID), January, 2019, Delhi.  [Online]:  https://ieeexplore.ieee.org/document/8710872
 
4. R. Yadav, S. Vidhyadharan, A. K. Shyam, M. P. Hirpara, T. Chaudhary, and S. S. Dan, "Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications," 32nd InternationalConference on VLSI Design and 18th International Conference on Embedded Systems (VLSID), January, 2019, Delhi. [Online]: https://ieeexplore.ieee.org/document/8711020
 
5. Simhadri Hariprasad, S. S. Dan, Ramakant Yadav, S. Vidhyadharan , “Innovative Strained SiGe Nanoscale Low & High V T Gate Overlap TFET Structures at 45 nm Standard CMOS Technology for Ultra-Low Power Yet High Performance Analog, Digital and Ternary VLSI Applications”, XX th International Workshop on Physics of Semiconductor Devices (IWPSD 2019), Kolkata.

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