Book Chapter
1. Chetan Vudadha and M. B. Srinivas (2018),
"Design of Ternary Logic Circuits Using CNFETs" In “Nanoscale
Devices: Physics, Modeling, and Their Application” by Kaushik, B. Boca
Raton: CRC Press, https://doi.org/10.1201/9781315163116
Journal Publications
7. S. Gadgil and C. Vudadha, "Novel Design Methodologies
for CNFET-Based Ternary Sequential Logic Circuits," in IEEE Transactions on Nanotechnology,
vol. 21, pp. 289-298, 2022, DOI: 10.1109/TNANO.2022.3184759. [SCI and Scopus Indexed; IF: 2.967]
6. Sai Phaneendra, P., Vudadha, C. & Srinivas, M.B. "Optimization of Reversible Circuits Using Gate Pair Classification". SN
COMPUT. SCI. 3, 40 (2022). DOI: 10.1007/s42979-021-00900-5. [Scopus Indexed; IF: NA]
5. S. Gadgil and C. Vudadha, "Design of CNTFET-Based
Ternary ALU Using 2:1 Multiplexer Based Approach," in IEEE
Transactions on Nanotechnology, vol. 19, pp. 661-671, Aug. 2020, DOI: 10.1109/TNANO.2020.3018867. [SCI and Scopus Indexed; IF: 2.967]
4. Chetan Vudadha, Ajay Surya K, Saurabh Agrawal and
M.B. Srinivas "Synthesis of Ternary Logic Circuits using 2:1
Multiplexers," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 65, no. 12, pp. 4313-4325, Dec. 2018. DOI: 10.1109/TCSI.2018.2838258. [SCI and Scopus Indexed; IF: 4.14]
3. Chetan Vudadha and M.B. Srinivas "Design of
High Speed and Power Efficient Ternary Prefix Adders using CNFETs,"
in IEEE Transactions on Nanotechnology, vol. 17, no. 4, pp.
772-782, July 2018. DOI: 10.1109/TNANO.2018.2832649. [SCI and Scopus Indexed; IF: 2.967]
2. Chetan Vudadha, P. S. Phaneendra and M. B. Srinivas
“Energy Efficient Design of CNFET-based Multi-Digit Ternary Adders," Microelectronics
Journal (Elsevier), Volume 75, pp. 75-86, May 2018. DOI:10.1016/j.mejo.2018.02.004. [SCI and Scopus Indexed; IF: 1.992]
1. C. Vudadha, S. Rajagopalan, A. Dusi, P. S.
Phaneendra and M. B. Srinivas, "Encoder-Based Optimization of CNFET-Based
Ternary Logic Circuits," in IEEE Transactions on Nanotechnology,
vol. 17, no. 2, pp. 299-310, March 2018. DOI: 10.1109/TNANO.2018.2800015. [SCI and Scopus Indexed; IF: 2.967]
Conference Publications
26. S. T, S. Gadgil and C. Vudadha, "Design of
CNTFET-based Ternary Logic circuits using Low power Encoder," 2022 IEEE
International Symposium on Smart Electronic Systems (iSES), Warangal, India,
2022, pp. 142-147.
25. S. V. Bharadwaj and C. K. Vudadha, "Evaluation of x86 and ARM architectures using compute-intensive workloads," 2022 IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 586-589.
24. S. Gadgil and C. Vudadha, "Design of CNFET-based Low-Power Ternary Sequential Logic circuits," 2021 IEEE 21st International Conference on Nanotechnology (NANO), 2021, pp. 169-172.
23. P. V. Bhanu, C. Vudadha and J. Soumya, "FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp. 1-5.
22. Harita Sirugudi, Sharvani Gadgil and Chetan Vudadha, "A Novel Low Power Ternary Multiplier Design using CNFETs," 2020 33rd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID), Bangalore, 2020
21. P. Patel, N. Doddapaneni, S. Gadgil, and C. Vudadha, " Design of Area Optimised, Energy efficient Quaternary Circuits using CNTFETs," 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Rourkela, India, 2019,
20. C. K. Vudadha and M.B. Srinivas, "Design Methodologies for Ternary Logic Circuits," 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), Linz, 2018, pp. 192-197.
19. Parlapalli, Sai Phaneendra; Vudadha, Chetan and Srinivas, M. B., "An ESOP Based Cube Decomposition Technique for Reversible Circuits", Reversible Computation, Springer International Publishing (2017), 127--140.
18. Parlapalli, Sai Phaneendra; Vudadha, Chetan and Srinivas, M. B., "Optimizing the Reversible Circuits Using Complementary Control Line Transformation", Reversible Computation, Springer International Publishing (2017), 111--126.
17. C. Vudadha, P. S. Phaneendra and M. B. Srinivas, "An Efficient Design Methodology for CNFET Based Ternary Logic Circuits," 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Gwalior, 2016, pp. 278-283.
16. Pal, Subhankar; Vudadha, Chetan; Phaneendra, P.Sai; Veeramachaneni, Sreehari; M.B. Srinivas, "A New Design of an N-Bit Reversible Arithmetic Logic Unit," in Fifth International Symposium on Electronic System Design (ISED), 2014 , vol., no., pp.224-225, 15-17 Dec. 2014.
15. Phaneendra, P.S.; Vudadha, C.; Sreehari, V.; Srinivas, M.B., "An Optimized Design of Reversible Quantum Comparator," 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 , vol., no., pp.557,562, 5-9 Jan. 2014.
14. Vudadha, C.; Katragadda, S.; Phaneendra, P.S., "2:1 Multiplexer based design for ternary logic circuits," IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2013 , vol., no., pp.46,51, 19-21 Dec. 2013
13. Vudadha, Chetan; Sai, Phaneendra P; Sreehari, V; Srinivas, M B;,"CNFET based ternary magnitude comparator," International Symposium on Communications and Information Technologies (ISCIT),2012, vol., no., pp.942-946, 2-5 Oct. 2012.
12. Vudadha, Chetan; Phaneendra, P. Sai; Sreehari, V.; Ahmed, Syed Ershad; Muthukrishnan, N. Moorthy; Srinivas, M.B.; , "Design of Prefix-Based Optimal Reversible Comparator," IEEE Computer Society Annual Symposium on VLSI (ISVLSI),2012, vol., no., pp.201-206, 19-21 Aug. 2012.
11. Vudadha, Chetan; Phaneendra, P. Sai; Sreehari, V.; Ahmed, Syed Ershad; Muthukrishnan, N. Moorthy; Srinivas, M.B.; , "Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders," IEEE Computer Society Annual Symposium on VLSI (ISVLSI),2012, vol., no., pp.225-230, 19-21 Aug. 2012.
10. Vudadha, Chetan; Sreehari, V.; Srinivas, M. B.; , "Multiplexer Based Design for Ternary Logic Circuits," ,2012 8th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), vol., no., pp.1-4, 12-15 June 2012.
09. Vudadha, C.; Phaneendra P, S.; Makkena, G.; Sreehari, V.; Muthukrishnan, N.M.; Srinivas, M.B.; , "Design of CNFET based ternary comparator using grouping logic," 2012 IEEE Faible Tension Faible Consommation (FTFC),, vol., no., pp.1-4, 6-8 June 2012.
08. Vudadha, C.; Makkena, G.; Nayudu, M.V.S.; Phaneendra, P.S.; Ahmed, S.E.; Veeramachaneni, S.; Muthukrishnan, N.M.; Srinivas, M.B.; , "Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs," 2012 25th International Conference on VLSI Design (VLSID), , vol., no., pp.280-285, 7-11 Jan. 2012.
07. Kumar, V. Chetan; Phaneendra, P. Sai; Ahmed, Syed Ershad; Sreehari, V.; Muthukrishnan, N. Moorthy; Srinivas, M.B.;, "A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block,"International Symposium on Electronic System Design (ISED), 2011, vol., no., pp.100-105, 19-21 Dec. 2011.
06. Chetan Kumar, V; Sai Phaneendra, P; Ershad Ahmed, S; Sreehari, V; Moorthy Muthukrishnan, N; Srinivas, M.B.; , "Higher radix sparse-2 adders with improved grouping technique," TENCON 2011 - 2011 IEEE Region 10 Conference , vol., no., pp.676-679, 21-24 Nov. 2011.
05. Phaneendra, P.S.; Vudadha, C.; Ahmed, S.E.; Sreehari, V.; Muthukrishnan, N.M.; Srinivas, M.B.; , "Increment/decrement/2's complement/priority encoder circuit for varying operand lengths," 11th International Symposium on Communications and Information Technologies (ISCIT), 2011 , vol., no., pp.472-477, 12-14 Oct. 2011.
04. Vudadha, C.; Veeramachaneni, S.; Srinivas, M.B.; "Non-linear partitioning for decimal logarithm approximation," Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2011 , vol., no., pp.102-105, 6-7 Oct. 2011.
03. Chetan Kumar, V.; Sai Phaneendra, P.; Ershad Ahmed, S.; Veeramachaneni, S.; Moorthy Muthukrishnan, N.; Srinivas, M.B.; , "A Prefix Based Reconfigurable Adder," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011, vol., no., pp.349-350, 4-6 July 2011.
02. Chetan Kumar, V.; Sai Phaneendra, P.; Ahmed, S.E.; Veeramachaneni, S.; Moorthy Muthukrishnan, N.; Srinivas, M.B.; , "A Unified Architecture for BCD and Binary Adder/Subtractor," 14th Euromicro Conference on Digital System Design (DSD), 2011, vol., no., pp.426-429, Aug. 31 2011-Sept. 2 2011.
01. Chetan Vudadha, Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, Moorthy Muthukrishnan and Srinivas M.B “An Improved Sum Computation Block for adders with High Sparseness ", in 20th International Workshop on Logic & Synthesis (IWLS 2011), June 2011, San Diego, CA, USA.